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PCI EXPRESSTM JITTER ATTENUATOR
ICS874001I-05
GENERAL DESCRIPTION
The ICS874001I-05 is a high performance Jitter IC S Attenuator designed for use in PCI ExpressTM sysHiPerClockSTM tems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874001I-05 has a bandwidth of 6MHz with <1dB peaking, easily meeting PCI Express Gen2 PLL requirements. The ICS874001I-05 uses IDT's 3rd Generation FemtoClock TM PLL technology to achive the lowest possible phase noise. The device is packaged in a small 20-pin TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards.
FEATURES
* One differential LVDS output pair * One differential clock input * CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Output frequency range: 98MHz - 640MHz * Input frequency range: 98MHz - 128MHz * VCO range: 490MHz - 640MHz * Cycle-to-cycle jitter: 50ps (maximum) * 3.3V operating supply * PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant * -40C to 85C ambient operating temperature * Available in lead-free (RoHS 6) package
PIN ASSIGNMENT
PLL_SEL nc nc nc MR nc F_SEL1 VDDA F_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nc VDDO Q nQ nc nc GND nCLK CLK OE
ICS874001I-05
20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View
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BLOCK DIAGRAM
PLL_SEL Pullup
0
CLK Pulldown nCLK Pullup
Phase Detector
VCO 490 - 640MHz
1
Output Divider 0 0 /5 0 1 /4 1 0 /2 (default) 1 1 /1
Q nQ
Internal Feedback
/5
MR
Pulldown 2
F_SEL[1:0] Pullup/Pulldown OE Pullup
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TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3, 4, 6, 15, 16, 20 5 7 8 9 10 11 12 13 14 17, 18 19 Name PLL_SEL nc Input Unused Type Pullup Description PLL select pin. When LOW, bypasses the PLL. When HIGH selects the PLL. LVCMOS/LVTTL interface levels. See Table 3B. No connect. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go LOW and the inver ted output nQ to go Pulldown HIGH. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C. Analog supply pin. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C. Core supply pin. Output enable. When HIGH, outputs are enabled. When LOW, forces Pullup outputs to a high impedance state. See Table 3A. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Power supply ground. Differential output pair. LVDS interface levels. Output supply pin.
MR F_SEL1 VDDA F_SEL0 VDD OE CLK nCLK GND nQ, Q VDDO
Input Input Power Input Power Input Input Input Power Output Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
Inputs OE 0 1 (default) Outputs Q , nQ High-Impedance Enabled
TABLE 3B. PLL _SEL CONTROL TABLE
0 = Bypass 1 = VCO (default)
TABLE 3C. F_SELX FUNCTION TABLE
Inputs F_SEL1 0 0 1 1 F_SEL0 0 1 0 1 Output Divider 5 4 2 1 Output Frequency Range (MHz) 98 - 128 122.5 - 160 245 - 320 (default) 490 - 640
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current 4.6V -0.5V to VDD + 0.5 V 10mA 15mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 86.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.0 VDD - 0.13 3.0 Typical 3.3 3.3 3.3 Maximum 3.6 VDD 3.6 75 13 25 Units V V V mA mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40C TO 85C
Symbol Parameter VIH VIL IIH IIL Input High Voltage Input Low Voltage Input High Current Input Low Current F_SEL1, OE, PLL_SEL F_SEL0, MR F_SEL1, OE, PLL_SEL F_SEL0, MR VDD = VIN = 3.6V VDD = VIN = 3.6V VDD = 3.6V, VIN = 0V VDD = 3.6V, VIN = 0V -150 -5 Test Conditions Minimum Typical 2 -0.3 Maximum VDD + 0.3 0.8 5 150 Units V V A A A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40C TO 85C
Symbol Parameter IIH IIL VPP Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VDD = VIN = 3.6V VDD = VIN = 3.6V VDD = 3.6V, VIN = 0V VDD = 3.6V, VIN = 0V -5 -150 0.15 GND + 0.5 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage; NOTE 1
VCMR Common Mode Input Voltage; NOTE 1, 2 NOTE 1: VIL must be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.20 1.35 Test Conditions Minimum 275 Typical 375 Maximum 485 50 1.50 50 Units mV mV V mV
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TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V 0.3V, TA = -40C TO 85C
Symbol fMAX Parameter Output Frequency Cycle-to-Cycle Jitter, NOTE 1 100MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 125MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 250MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 500MHz, (1.2MHz -21.9MHz), Evaluation Band: 0Hz - Nyquist (clock frequency/2) 100MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 125MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 250MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 500MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 100MHz output, Low Band: 10kHz - 1.5MHz 125MHz output, Low Band: 10kHz - 1.5MHz 250MHz output, Low Band: 10kHz - 1.5MHz 500MHz output, Low Band: 10kHz - 1.5MHz 20% to 80% F_SEL[10] 11 Test Conditions Minimum 98 Typical Maximum 640 50 16.14 Units MHz ps ps
tjit(cc)
15.64
ps
Tj
Phase Jitter Peak-to-Peak; NOTE 2, 4
13.16
ps
12.17
ps
1.4
ps
1.39
ps
TREFCLK_HF_RMS
Phase Jitter RMS; NOTE 3, 4
1.18
ps
1.11 0.33 0.22 0.22 0.22 200 48 600 52
ps ps ps ps ps ps %
TREFCLK_LF_RMS
Phase Jitter RMS; NOTE 3, 4
tR / tF odc
Output Rise/Fall Time Output Duty Cycle
F_SEL[10] = 11 42 58 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditons. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Peak-to-peak jitter after system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. See IDT Application Note,PCI Express Reference Clock Requirements and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. NOTE 3: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and repor ting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). See IDT Application Note,PCI Express Reference Clock Requirements and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. NOTE 4: Guaranteed only when input clock source is PCI Express and PCI Express Gen 2 compliant.
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PARAMETER MEASUREMENT INFORMATION
VDD
SCOPE
3.3V0.3V POWER SUPPLY + Float GND -
VDD, VDDO
Qx
VDDA
nCLK
V
PP
LVDS
nQx
Cross Points
V
CMR
CLK
GND
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQ Q
nQ
t PW
t
PERIOD
Q
tcycle n
odc =
t PW t PERIOD
x 100%
tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
CYCLE-TO-CYCLE JITTER
VDD
nQ
80%
80% VOD
DC Input
LVDS
Q
tR
tF
out
OUTPUT RISE/FALL TIME
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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20%
20%
tcycle n+1
out
100
VOD/ VOD
ICS874001I-05 PCI EXPRESSTM JITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION, CONTINUED
VDD out
DC Input
LVDS
out
VOS/ VOS
OFFSET VOLTAGE SETUP
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APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS874001I-05 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that V DDA requires that an additional10 resistor along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to
the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
2.5V
3.3V
2.5V 3.3V 2.5V
*R3
33
Zo = 50
R3 120 Zo = 60
R4 120
CLK
CLK
Zo = 50 nCLK
Zo = 60 nCLK
HCSL
*R4
33 R1 50 R2 50
HiPerClockS Input
SSTL
R1 120 R2 120
HiPerClockS
*Optional - R3 and R4 can be 0
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER
FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER
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RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS:
LVCMOS CONTROL PINS All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V 50
LVDS Driver R1 100
+
-
50
100 Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
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SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS874001I-05 application schematic. In this example, the device is operated at VDD = 3.3V. The decoupling capacitors should be located as close
U1 VDDO = 3.3V PLL_SEL VDD = 3.3V MR F_SEL1 VDD 10 R2 C1 0.1u C2 10u VDDA F_SEL0 1 2 3 4 5 6 7 8 9 10 PLL_SEL nc nc nc MR nc F_SEL1 VDDA F_SEL0 VDD nc VDDO Q nQ nc nc GND nCLK CLK OE 20 19 18 17 16 15 14 13 12 11 VDDO Q nQ GND nCLK CLK OE nQ Q + R1 100 Zo = 50 Ohm Zo = 50 Ohm
as possible to the power pin. The input is driven by a 3.3V LVPECL driver.
Zo = 50 Ohm
Zo = 50 Ohm
LVPECL Driv er
R6 50
R7 50 Q
Zo = 50 Ohm
Logic Control Input Examples
VDD
VDDO (U1:19) R8 50 C5 .1uf
VDD(U1:10)
R4 50
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 Not Install
+
C6 10uf
C7 .1uf C3 0.1uF R5 50 -
Zo = 50 Ohm nQ
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
Alternate LVDS Termination
FIGURE 5. ICS874001I-05 SCHEMATIC LAYOUT
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PCI EXPRESS APPLICATION NOTE
PCI Express jitter analysis methodology models the system response to reference clock jitter. The below block diagram shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided ot both ends of the PCI Express Link. In the jitter analysis, the Tx and Rx serdes PLLs are modeled as well as the phase interpolator in the receiver. These ransfer functions are called H1, H2 and H3 respectively. The overall system transfer function at the receiver is: Ht(s) = H3(s) * [H1(s) - H2(s)] The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y(s) = X(s) * H3(s) * [H1(s) - H2(s)] In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s) * H3(s) * [H1(s) - H2(s)]. For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz to 50MHz) and the jitter result is reported in peak-peak. For PCI Express Gen2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz - Nyquist (High Band). The below plots show the individual transfer functions as function H1, F2 for H2, and f# for H3. For a more thorough overivew of PCI Express jitter analysis methodology, please refer to IDT Application Note, PCI Express Reference Clock Requirements.
Tx Serdes Rx Serdes D 2.5 GHz PLL x25 Mult H1(s) 100 MHz X(s) Phase Aligner H3(s)
Y(s)
Q
PLL x25 Mult H2(s) 2.5 GHz
100 MHz X(s)
Reference Clock System Transfer Function, Ht(s) = H3(s) * [H1(s) - H2(s)] Reference Clock Spectrum seen by Receiver Sample Latch, Y(s) = X(s) * Ht(s)
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PCIe GEN 1 MAGNITUDE OF TRANSFER FUNCTION
PCIe GEN 2A MAGNITUDE OF TRANSFER FUNCTION
PCIe GEN 2B MAGNITUDE
OF TRANSFER
FUNCTION
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS874001I-05. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS874001I-05 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results.
* *
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.6V * (75mA + 13mA) = 316.8mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.6V * 25mA = 90mW
Total Power_MAX = 316.8mW + 90mW = 406.8mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 86.7C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.407W * 86.7C/W = 120.3C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board.
TABLE 6. THERMAL RESISTANCE JA FOR 20-LEAD TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 86.7C/W
1
82.4C/W
2.5
80.2C/W
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RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 86.7C/W
1
82.4C/W
2.5
80.2C/W
TRANSISTOR COUNT
The transistor count for ICS874001I-05 is: 1608
PACKAGE DIAGRAM
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
AND
DIMENSIONS
TABLE 8. PACKAGE DIMENSIONS
SYMBOL MIN N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 20 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX
Reference Document: JEDEC Publication 95, MO-153
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TABLE 9. ORDERING INFORMATION
Part/Order Number 874001AGI-05LF 874001AGI-05LFT Marking ICS4001AI05L ICS4001AI05L Package 20 Lead "Lead-Free" TSSOP 20 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel Temperature -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA)
(c) 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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